1. Field of the Invention
The present invention relates to a memory device and in particular, a nonvolatile memory device and a method of programming and/or verifying the same.
2. Background of the Related Art
The packing density of a conventional nonvolatile memory corresponds in a one to one fashion to the number of memory cells. When nonvolatile semiconductor memory devices, such as EEPROM and flash EEPROM, are used as mass storage media, it is difficult to overcome the high cost-per-bit of the memories. Further, nonvolatile memory chips of low power consumption are required for application of the nonvolatile memories to portable products. In order to lower the cost-per-bit, multibit-per-cell has been actively studied.
A multibit cell stores data of over two bits in one memory cell to enhance the density of data on the same chip area without increasing the size of the memory cell. In order to implement a multibit cell, more than two threshold voltage levels may be programmed on each memory cell. For example, in order to store data of two bits for every cell, the respective cells must be programmed in 2.sup.2 (four) threshold levels. The four threshold levels correspond to logic states 00, 01, 10, and 11, respectively. However, a problem arises due to statistical distribution value of about 0.5 V during the multi-level programming.
The distribution is reduced by precisely setting the respective threshold levels, and more levels can be programmed, which increases the number of bits per cell. To reduce the voltage distribution, repeated programming and verification are performed in the conventional method. For programming, a series of voltage pulses are applied to the cells to adjust the threshold levels. To verify whether a cell has reached an intended threshold level, a read operation is performed between the respective programming voltage pulses. Programming and verification are completed when the verified threshold level reaches the intended threshold level.
In the conventional method of repeated programming and verification, there is some difficulty in reducing the error distribution of the threshold level due to the limited pulse width of a program voltage. Further, the algorithm of repeated programming and verification is implemented with additional circuits, which increase the area of peripheral circuits on the chip. The repetitive method prolongs the programming time. To solve such problems, R. Cernea of SunDisk Co., Ltd. suggested a method of simultaneous programming and verification in U.S. Pat. No. 5,422,842.
FIG. 1A illustrates the symbol and circuit diagram of the nonvolatile memory. The nonvolatile memory cell includes a control gate 1, floating gate 2, source 3, channel area 4, and drain 5. When voltages sufficient to cause programming are applied to control gate 1 and drain 5, a current flows between drain 5 and source 3, and electrons are injected into the floating gate 2. This current is compared to a reference current, which varies for each threshold voltage level to be programmed. The auto verification of a programmed condition at the same time as programming can compensate for the disadvantage of the repetition of the program verification to some extent. When the current reaches a value equal to or smaller than the reference current, a programming completion signal is produced.
U.S. Pat. No. 5,043,940 discloses a method for conducting multi-level programming in which voltages applied to each terminal of the memory cell are fixed while reference currents for respective levels are varied. In these methods, as shown in FIG. 1B, the relation between the reference currents for detection and the cell threshold voltages is neither explicit nor linear.
In the above method, the threshold level is not adjusted by a voltage applied to the control gate of the memory cell. Hence, a separate optimization of the operations for programming and sensing is difficult. The unseparated currents for programming and monitoring prevent direct control of the threshold voltage of cell. Accordingly, a current controlled type programming method like aforementioned prior arts has a disadvantage that a direct and effective multi-level control is also difficult.
To eliminate such problems, the present inventor suggested a programming method of a voltage control type in which precise control of the threshold voltage of a multibit cell is done by means of a voltage applied to the control gate of the cell (U.S. patent application Ser. No. 08/542,651, commonly assigned to the same assignee). According to this method, a shift of the threshold voltage of a cell is precisely identical to a shift of the control gate voltage. Therefore, the threshold voltage can be ideally adjusted. However, a channel of the transistor is turned on at the start of programming (i.e., inverted) for current flow therethrough, and a current at a drain is decreased, as the programming proceeds, until the current flow level reaches a predetermined reference current value. Since the current flow starts at the maximum current from the start of programming and decreases thereafter, the initial power consumption is high.
The cell structures of EEPROM and flash EEPROM can be classified into two types, according to the position of floating gate on the channel region. The first type is the simple stacked gate structure in which the floating gate fully covers the channel region. The second type is the split-channel structure in which the floating gate covers only a portion of the channel region between the source and drain. The channel region not covered by the floating gate thereon is functionally called a select transistor. The select transistor and the floating gate transistor are connected in series to compose a memory cell.
The split-channel type cell is also classified into two different types according to the methods for forming the select transistor. A merged-split-gate cell has a control gate electrode of the floating gate transistor and a gate electrode of the select transistor integrated into one. A split-gate-cell has the control gate electrode of the floating gate transistor and the gate electrode of the select transistor separated from each other. The select transistor prevents the problem of over erasure and allows easy formation of contactless virtual ground array. The split-gate-cell allows easier hot electron injection from the source side.
FIG. 2A illustrates a diagram of a conventional nonvolatile memory cell of simple stacked gate type, and FIG. 2B illustrates a diagram of a conventional nonvolatile memory cell of split channel type. FIGS. 2A and 2B also illustrate the program and erasure mechanisms. In FIG. 2A, the stacked gate type cell comprises a control gate 6, a floating gate 7, a source 8, a drain 9, a channel region 10 and a gate 11 for use in erasure. In FIG. 2B, the split channel type cell comprises a control gate 13, a floating gate 14, a source 15, a drain 16, a channel region 17 and a gate 18 for use in erasure.
The split-channel cell employs a hot electron injection mechanism for programming the threshold voltage level. The merged-split-gate cell employs a drain side hot electron injection mechanism while the split-gate cell employs a source side hot electron injection mechanism. The split-channel cell has more power consumption due to the hot electron injection mechanism used during programming operation compared to tunneling mechanism. There is difficulty in the merged-split-gate cell in carrying out different kinds of ion injection two times into the drain region, as required for better hot carrier injection. There is difficulty in the split-gate cell for optimizing an oxide film thickness between the select transistor and the floating gate transistor, which is required for better hot carrier injection, for appropriate flow of current during an initial read operation and for preventing the degradation of the read current caused by degradation of the oxide film.
In the conventional split-channel cell, the electron injection (programming=data writing) is carried out by hot carrier injection through a gate oxide film adjacent to a channel. The electron erasure (deletion of data) is carried out either through a third gate other than a select gate or the control gate, or through a gate oxide film adjacent to a channel, or through the control gate.
Similar to other EEPROMs, FN-tunneling is employed for erasure. In case of the aforementioned split-channel cell, a thin gate insulating film of about 100 .ANG. is required since the cell uses tunneling through the insulating film for erasure. The thin insulating film cannot assure reliable operation and degrades control gate coupling. In other words, as the cell size is further reduced, the coupling becomes even smaller, which is not favorable for low voltage/high speed operation.
Further, the erasure gates 11 and 18 are not necessary during the programming operation, and each of the conventional cells, shown in FIGS. 2A and 2B, has a structure equivalent to a double polygate structure. Conventionally, the programming operation is conducted using only electrodes of the control gate, source and/or drain, and the current paths for programming and verifying (or sensing) within a memory cell are unseparated, such that a direct and effective multi-level control has been difficult.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.